Madesh Eswaran

 Extensive knowledge of synthesis and implementation concepts in vivado tool
 Good knowledge in modelling of components in matlab with xilinx blockset.
 Hands-on experience in RTL coding in verilog and vhdl, FPGA design flow including synthesis, place and route and System Level Debugging.
 In-depth knowledge in FPGA pin planning for new designs and clock requirements for FPGA.
 Good experience in integration and implementation of RTL modules and on board testing.
 Experience of using real time debugging tools like Xilinx Chip Scope Pro and Logic Analyser.
 Hands-on experience in working with the tools like XILINX Ise/Vivado.
 Planned and organized design projects/phases of design projects.
 Hands-on experience in Timing Contraints, floor planning, routing, and logic equivalency and mapping, Frequency enhancement methodology.
 Experience in Digital Logic Design and Static Timing Analysis.
 Immense ability to resolve non-functional errors, syntax errors in RTL, and take block through synthesis, place and route, timing closure.
 Good control on Verilog HDL in the RTL synthesis point of view.
 Supported to Hardware Team for FPGA Board development
 Self-driven and has the ability to work independently as well as in team environment.