Rahul Shah

4+ years of experience in VLSI – Design, Architecture, FPGA, ASIC, Validation, Testing, Integration.
Experience of memory protocols – HBM, LPDDRx and DDRx and DFI; AMBA protocols – AXI,
AHB and APB. Knowledge of PCIe and RapidIO protocols.
Extensive experience in IP architecture and micro architecture. Developed IP for DDRx/LPDDRx controller and Traffic Generator.
Experience of designing in highly reusable/parameterized HDL coding style using Verilog/VPP.
Designed complex and pipelined micro architecture for FPGA and ASIC.
Experience of Altera Quartus II and its tools. Complete knowledge of Altera IP (UniPHY, EMIF,
Nios II, Transceiver Native PHY, PIPE, etc.). Worked on Arria 10, Stratix V, Arria V and Cyclone V.
Experience of Xilinx Vivado. Worked on MIG, Microblaze, etc. Worked on Artix 7 and Kintex 7.
Validation experience of block level as well as system level of various DUTs.
Verification experience at block level and system level using Questasim, VCS and NCsim.
Experience of C programming to generate executable and link format (.elf) file to work with Nios II
processor (Altera) and Microblaze (Xilinx). Worked on Eclipse and Xilinx SDK.
Integration experience using Altera Qsys and Xilinx IP Integrator.