Gaurav Mishra

I have completed 5-year Integrated Dual Degree with Bachelors in ECE and Masters in VLSI Design with 7.79 CGPA in the session of 2011-2016.

Through external exposure and academics curriculum, i have been well versed with the concepts of programming and data structures.

I have done research projects on various analog circuits and thus have a substantive knowledge in full custom (transistor level) CMOS VLSI circuit design and layout techniques.

I also have done coursework in digital design through verilog and have substantive information about interconnects protocols like AMBA AHB, APB etc. Verilog : Intermediate; System Verilog: Beginner.

Specialities

Cadence Virtuoso (Analog IC design, Simulation, Layout and Post-Layout Techniques), Verilog(Intermediate level), System Verilog (Basic Level), C (Intermediate Level), C++(Basic Level) MATLAB.

Exposure :

Summer Intern at Center for Electronic Test Engineering, STQC, Govt. of India.

Course in Advanced Embedded system and Image Processing with Matlab @Robospecies Technologies.

Course in System Verilog @3ST Technologies.

Projects

1) Wireless Power Transfer System (Minor Project)

2) Capacitor-less Low Drop-out Voltage regulator for SoC Applications in 180nm standard CMOS Technology. (Major Project)

3) Design and Verification of AMBA - Advanced High Performance Bus (AHB) Protocol in Verilog.