Not Specified
Full Time
View Applications
Skills
RTL SoC ASIC Verilog VHDL RTL Coding RTL Design SoC Design- Experience
- 4 to 6 Years
- Industry
- IT - Software Services
- Functional Area
- R&D / Engineering Design
Requirements:
- Digital Micro-architecture of complex IP and/or ASIC blocks
- Experience creating Verilog based designs from Scratch
- Experience developing AXI based IPs/ Blocks
- Good Lint/CDC/Synthesis check experience.
- Company
- Mobiveil India Technologies Private Limited
- Location
- Mobiveil India Technologies Private Limited
Chennai - Website
- http://www.mobiveil.com
- View Jobs By This Company
Similar Jobs
Posted By
