Not Specified
Full Time
View Applications
Skills
RTL SoC ASIC Verilog VHDL RTL Coding RTL Design SoC Design- Experience
- 8 to 10 Years
- Industry
- IT - Software Services
- Functional Area
- R&D / Engineering Design
Requirements:
- Minimum 8+ experience in RTL 2 GDSII Design
- Experience in Sub-micron Physical design methodologies and Physical Verification
- Should have exposure in Synthesis / DFT / Logical equivalence check
- Experience in Synopsys Flow
- Experience in block/full chip level Floorplan, Power grid and Clock tree design, Place & Route and Physical verification
- Company
- Mobiveil India Technologies Private Limited
- Location
- Mobiveil India Technologies Private Limited
Chennai - Website
- http://www.mobiveil.com
- View Jobs By This Company
Similar Jobs
Posted By
